1. Field of the Invention
The present invention relates to a semiconductor memory device.
Generally, a semiconductor memory device comprises a word-line selecting and driving circuit (word drive circuit) for decoding word address signals to select a single word line and for driving the selected single word line, a bit-line selecting circuit for decoding bit address signals, a plurality of word lines connected to the outputs of the word-drive circuit, a plurality of bit lines connected to the outputs of the bit-line selecting circuit, and memory cells arranged on the intersections between the word lines and the bit lines.
The present invention more particularly relates to a semiconductor memory device in which the memory cell array can be miniaturized without limitation by the space occupied by the word drive circuit.
2. Description of the Prior Art
Conventionally, the outputs of a word drive circuit are connected to the word lines in a one-to-one correspondence. Recent miniaturization of memory cells has led to an increasingly smaller space between adjacent word lines; however, this has made essential the miniaturization of the word drive circuit which is integrated with the memory cell array on one chip. Miniaturization of word drive circuits, however, is difficult.
As a result, the size of the word drive circuits has limited the degree to which memory cell arrays could be miniaturized. This has been especially true in an erasable programmable read only memory (EPROM) which has a complicated word drive circuit including high voltage driving circuits as well as row decoder circuits. Therefore, in conventional semiconductor memory devices, although the size of the memory cell arrays themselves could theoretically be miniaturized, the degree of their miniaturization has been limited by the size of the word drive circuits. As a result, the total size of semiconductor memory devices could not be miniaturized to the desired extent.
To achieve some miniaturization of semiconductor memory devices, one known system has had the word drive circuits arranged on both sides of the memory cell arrays. While this system does allow the memory cell arrays to be miniaturized, it doubles the area occupied by the word drive circuits compared with a system where the word drive circuits are arranged on only one side of the memory cell array. Therefore, this known system runs counter in principle to the miniaturization of the entire semiconductor memory device.